Members: Abraham KleinHS, Dhruv RamaswamyUG, Rishabh RamaswamyHS, Charles YuHS
Advisor: Dr. Richard Martin
Our project aims to demonstrate a proof of concept for implementing neural network inference on an FPGA using both CaST and SystemVerilog. We will verify that a trained neural network can execute correctly in hardware and evaluate its inference capabilities by measuring performance and resource utilization. This comparison will help assess the feasibility of using CaST as a hardware design approach for neural network acceleration.
- Placeholder
- Thursday Presentation
- Progress
- First week for high school interns. During the week, we learned the basics of neural networks and FPGA hardware. In addition, we went through a System Verilog tutorial and started programming simple System Verilog modules.
- Thursday Presentation
- Progress
- High School interns: Finished System Verilog tutorial modules, ending with a matrix multiplier and filter program. Also learned basics of CaST, the high-level alternative to System Verilog.
- Thursday Presentation
- Progress
- High School Interns: Started programming systolic matrix multiplication program in CaST. Also started debugging CaST compiler by fixing the implementations for arrays, loops, and inter-machine communication.
- Thursday Presentation
- Progress
- High School Interns: Able to get updated CaST compiler working on terminal with working implementations for arrays, loops, and inter-machine communication. Also finished Hexagonal Systolic Matrix multiplication program in CaST.
- Progress
- High School Interns: Created simple MNIST Multi-Layer Perceptron that utilized our Hexagonal Systolic Matrix Multiplication CaST program. Achieved 96% training accuracy and 98% test accuracy with 529.81 clock cycles per image.
- Final Presentation